A simple but effective little module. An active buffer build around the TL074 & TL072 IC’s. The output of the last output of the first block is linked to the input of the second block. So when there is nothing connected to the second input you have a 1×7 buffer.
Ps. On the silkscreen is a small typo; it should note “2×3 / 1×7” instead of “2×3 / 1×6”, this is fixed in the schematics & PCB design.